In a general semiconductor integrated circuit producing process, as illustrated in FIG. 7, first, a light-exposing treatment for irradiating a wafer covered with barrier metal with light to form a wiring pattern thereon is performed and then an edging treatment for forming wiring grooves in accordance with the wiring pattern formed by light irradiation is performed. Next, after performing a plating treatment for accumulating copper on the entire surface of the wafer to form a copper-plated film, a polishing treatment for scraping the copper-plated film until the barrier metal appears in a predetermined position on the wafer is performed. Then, an over polishing treatment for scraping an extra copper-plated film accumulated on a portion other than portions under which the wiring grooves are formed (hereinafter, referred to as wiring-groove-formed portions) is performed.
Incidentally, in the case that a state that a copper-plated film remains on a portion other than the wiring-groove-formed portions (that is, a copper residue remains) is observed as illustrated in FIG. 8 after the over polishing treatment has been performed, such trouble may sometimes occur that short-circuiting generates in wiring of a resultant product and hence production yield thereof is decreased. Thus, in order to avoid the above mentioned trouble, prior to production of a circuit, whether a copper residue will generate upon production of the circuit under producing conditions set by a user is evaluated. In the case that it has been evaluated that the copper residue will generate, for example, producing conditions are corrected to increase the thickness of a copper-plated film to reduce a difference in height among copper-plated films obtained after a plating treatment has been performed thereon, thereby avoiding generation of the copper residue.
In this connection, techniques for simulating a semiconductor integrated circuit producing process to predict a result of polishing are disclosed in Japanese Laid-Open Patent Publication Nos. 2004-40004 and 2003-224098, Jianfeng Luo and three others, “A Layout Dependent Full-Chip Copper Electroplating Topography Model”, International Conference on Computer-Aided Design, 2005, T. Tugbawa, “Chip-Scale Modeling of Pattern Dependencies in Copper Chemical Mechanical Polishing Processes”, PhD thesis, Massachusetts Institute of Technology, 2002, and D. Fukuda and three others, “Full-Chip CMP Simulation System”, International Conference on Planarization/CMP Technology, 2007.
However, the related art disclosed in the above mentioned literatures has such a problem that it takes much time to calculate an optimum thickness of a copper-plated film. That is, every time the thickness of a copper-plated film is corrected, simulation of a producing process from the start of a plating treatment to the completion of an over polishing treatment is repeatedly executed and hence such trouble may occur that extra much time is needed to calculate even a copper-plated film thickness with which any copper residue does not generate.